Final PCB Error Checklist - Revision history

Smaldonado: Added my most embarrassing moment as an EE

2016-09-23T08:20:34Z

Added my most embarrassing moment as an EE

← Older revision		Revision as of 08:20, 23 September 2016
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	\|Check ICs to make sure all pins are routed or appropriately not connected. Avoid setting the schematic editor snap grid to anything other than 10 [units].		\|Check ICs to make sure all pins are routed or appropriately not connected. Avoid setting the schematic editor snap grid to anything other than 10 [units].
	\|Kirill Safin, on HAB Main Avionics PoS1, where a number of pins appeared connected but were very much not.		\|Kirill Safin, on HAB Main Avionics PoS1, where a number of pins appeared connected but were very much not.

			\|-
			\|rowspan="1"\|Routing Errors
			\|Sensitive Analog Traces Near Noise Sources
			\|When a trace carrying an analog voltage - i.e. a voltage or current sense - is routed in a way that makes it likely to pick up noise, affecting the analog value.
			\|Route sensitive analog lines first, shielded by ground planes when appropriate, and then be mindful of the placement of noise-inducing devices (i.e. inductors). On two-layer boards, cross traces on opposite layers at right angles to each other to minimize noise coupling.
			\|Sasha Maldonado, on ValBal Generation V.I, where a voltage sense line was run ''under'' and '''parallel to''' an inductor in a switching power converter, creating a small transformer and rendering the voltage sense useless.
			\|-

	\|-		\|-

Smaldonado: Added silkscreen errors.

2016-06-24T06:47:14Z

Added silkscreen errors.

← Older revision		Revision as of 06:47, 24 June 2016
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	\|rowspan="2"\|Schematic Errors		\|rowspan="2"\|Schematic Errors
	\|Inconsistent Net Naming		\|Inconsistent Net Naming
	\|When two nodes must be electrically connected but aren't visually connected in the schematic by a single wire, naming their nets two different things and causing there to be no connection, leading to a trace not being placed		\|When two nodes must be electrically connected but aren't visually connected in the schematic by a single wire, naming their nets two different things and causing there to be no connection, leading to a trace not being placed.
	\|Check ICs to make sure all pins are routed or appropriately not connected		\|Check ICs to make sure all pins are routed or appropriately not connected.
	\|Sasha Maldonado, on ValBal Generation IV, where the chip select for an SD card was labeled "SDCS" at one point and "CS" at another		\|Sasha Maldonado, on ValBal Generation IV, where the chip select for an SD card was labeled "SDCS" at one point and "CS" at another.
	\|-		\|-

	\|Wires and Pins Not Aligned On Grid		\|Wires and Pins Not Aligned On Grid
	\|Improperly setting the snap grid in the schematic editor, such that wires and pins can appear connected at a quick glance but not actually be connected, leading to a trace not being placed		\|Improperly setting the snap grid in the schematic editor, such that wires and pins can appear connected at a quick glance but not actually be connected, leading to a trace not being placed.
	\|Check ICs to make sure all pins are routed or appropriately not connected. Avoid setting the schematic editor snap grid to anything other than 10 [units]		\|Check ICs to make sure all pins are routed or appropriately not connected. Avoid setting the schematic editor snap grid to anything other than 10 [units].
	\|Kirill Safin, on HAB Main Avionics PoS1, where a number of pins appeared connected but were very much not		\|Kirill Safin, on HAB Main Avionics PoS1, where a number of pins appeared connected but were very much not.

			\|-
			\|rowspan="2"\|Silkscreen Errors
			\|Silkscreen Over Pads/Vias
			\|When silkscreen - a line, part label, etc - is place over an etched pad or a via and therefore doesn't fully print.
			\|Visualize the board in 3D {{altium-shortcut\|3}}, where intersections between silkscreen and board features are more obvious.
			\|Sasha Maldonado, on ValBal Generation V, where multiple part labels were printed over exposed copper and so were awkwardly clipped - some to the point of being nonfunctional.
			\|-

			\|Failure to Place Information on Board
			\|Not placing the standard set of silkscreen features on a board - board name, designer name(s), date, revision, sponsor logos, SSI logo. "Made with <3 in Stanford, CA" is hardly required but encouraged.
			\|Just do it. Seriously. Your work takes a bunch of your time. It should look good.
			\|Cameron Ramos, who did none of this on the Can Transceiver Board v2.
	\|}		\|}

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Smaldonado: Created page with "The following is a collection of errors that have previously been made in SSI PCBs. It is presented here so that future boards have a list of errors to check for, to a..."

2016-06-14T00:51:11Z

Created page with "The following is a collection of errors that have previously been made in SSI PCBs. It is presented here so that future boards have a list of errors to check for, to a..."

New page

The following is a collection of errors that have previously been made in SSI [[PCB|PCBs]]. It is presented here so that future boards have a list of errors to check for, to avoid fates ranging from embarrassment to system failure. '''It is encouraged that all SSI PCB designers check through this list prior to generating design files for a board.'''

{| class="wikitable" style = "width:100%"
{{red-header|columns=5|size = 110}}SSI Hall of Coaster-makers
|-
|'''Category'''
|'''Error'''
|'''Description'''
|'''Solution'''
|'''Notable Entrant'''
|-
|rowspan="2"|Schematic Errors
|Inconsistent Net Naming
|When two nodes must be electrically connected but aren't visually connected in the schematic by a single wire, naming their nets two different things and causing there to be no connection, leading to a trace not being placed
|Check ICs to make sure all pins are routed or appropriately not connected
|Sasha Maldonado, on ValBal Generation IV, where the chip select for an SD card was labeled "SDCS" at one point and "CS" at another
|-

|Wires and Pins Not Aligned On Grid
|Improperly setting the snap grid in the schematic editor, such that wires and pins can appear connected at a quick glance but not actually be connected, leading to a trace not being placed
|Check ICs to make sure all pins are routed or appropriately not connected. Avoid setting the schematic editor snap grid to anything other than 10 [units]
|Kirill Safin, on HAB Main Avionics PoS1, where a number of pins appeared connected but were very much not
|}

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