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| |rowspan="2"|Schematic Errors | | |rowspan="2"|Schematic Errors |
| |Inconsistent Net Naming | | |Inconsistent Net Naming |
− | |When two nodes must be electrically connected but aren't visually connected in the schematic by a single wire, naming their nets two different things and causing there to be no connection, leading to a trace not being placed | + | |When two nodes must be electrically connected but aren't visually connected in the schematic by a single wire, naming their nets two different things and causing there to be no connection, leading to a trace not being placed. |
− | |Check ICs to make sure all pins are routed or appropriately not connected | + | |Check ICs to make sure all pins are routed or appropriately not connected. |
− | |Sasha Maldonado, on ValBal Generation IV, where the chip select for an SD card was labeled "SDCS" at one point and "CS" at another | + | |Sasha Maldonado, on ValBal Generation IV, where the chip select for an SD card was labeled "SDCS" at one point and "CS" at another. |
| |- | | |- |
| | | |
| |Wires and Pins Not Aligned On Grid | | |Wires and Pins Not Aligned On Grid |
− | |Improperly setting the snap grid in the schematic editor, such that wires and pins can appear connected at a quick glance but not actually be connected, leading to a trace not being placed | + | |Improperly setting the snap grid in the schematic editor, such that wires and pins can appear connected at a quick glance but not actually be connected, leading to a trace not being placed. |
− | |Check ICs to make sure all pins are routed or appropriately not connected. Avoid setting the schematic editor snap grid to anything other than 10 [units] | + | |Check ICs to make sure all pins are routed or appropriately not connected. Avoid setting the schematic editor snap grid to anything other than 10 [units]. |
− | |Kirill Safin, on HAB Main Avionics PoS1, where a number of pins appeared connected but were very much not | + | |Kirill Safin, on HAB Main Avionics PoS1, where a number of pins appeared connected but were very much not. |
| + | |
| + | |- |
| + | |rowspan="1"|Routing Errors |
| + | |Sensitive Analog Traces Near Noise Sources |
| + | |When a trace carrying an analog voltage - i.e. a voltage or current sense - is routed in a way that makes it likely to pick up noise, affecting the analog value. |
| + | |Route sensitive analog lines first, shielded by ground planes when appropriate, and then be mindful of the placement of noise-inducing devices (i.e. inductors). On two-layer boards, cross traces on opposite layers at right angles to each other to minimize noise coupling. |
| + | |Sasha Maldonado, on ValBal Generation V.I, where a voltage sense line was run ''under'' and '''parallel to''' an inductor in a switching power converter, creating a small transformer and rendering the voltage sense useless. |
| + | |- |
| + | |
| + | |- |
| + | |rowspan="2"|Silkscreen Errors |
| + | |Silkscreen Over Pads/Vias |
| + | |When silkscreen - a line, part label, etc - is place over an etched pad or a via and therefore doesn't fully print. |
| + | |Visualize the board in 3D {{altium-shortcut|3}}, where intersections between silkscreen and board features are more obvious. |
| + | |Sasha Maldonado, on ValBal Generation V, where multiple part labels were printed over exposed copper and so were awkwardly clipped - some to the point of being nonfunctional. |
| + | |- |
| + | |
| + | |Failure to Place Information on Board |
| + | |Not placing the standard set of silkscreen features on a board - board name, designer name(s), date, revision, sponsor logos, SSI logo. "Made with <3 in Stanford, CA" is hardly required but encouraged. |
| + | |Just do it. Seriously. Your work takes a bunch of your time. It should look good. |
| + | |Cameron Ramos, who did none of this on the Can Transceiver Board v2. |
| |} | | |} |
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| {{altium-stub}} | | {{altium-stub}} |
| [[Category:Altium]] | | [[Category:Altium]] |